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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. a 10/06/02 is 61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? copyright ? 2002 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? internal self-timed write cycle individual byte write control and global write clock controlled, registered address, data and control interleaved or linear burst sequence control using mode input three chip enable option for simple depth expansion and address pipelining common data inputs and data outputs jedec 100-pin tqfp and 119-pin pbga package power supply + 3.3v v dd + 3.3v or 2.5v v ddq (i/0) snooze mode for reduced-power standby t version (three chip selects) j version (pbga package with jtag) d version (two chip selects) jtag boundary scan for pbga. 256k x 32, 256k x 36, 512k x 18 synchronous flow - through static ram october 2002 fast access time symbol parameter 6.5 7.5 units t kq clock access time 6.5 7.5 ns t kc cycle time 7.5 8.5 ns frequency 133 117 mhz description the issi is61lf25632, is61lf25636, and is61lf51218 are high-speed, low-power synchronous static rams designed to provide a burstable, high-performance and memories for commucation and networking applications. the is61lf25632 is organized as 262,144 words by 32 bits and the is61lf25636 is organized as 262,144 words by 36 bits. the is61lf51218 is organized as 524,288 words by 18 bits. fabricated with issi 's advanced cmos technology, the device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers that are controlled by a positive-edge- triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be from one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. byte write operation is performed by using byte write enable ( bwe ).input combined with one or more individual byte write signals ( bwx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write controls. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated internally and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence order, linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left floating.
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? block diagram binary counter bwa gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 16/17 18/19 address register ce d clk q dqd byte write registers d clk q dqc byte write registers d clk q dqb byte write registers d clk q dqa byte write registers d clk q enable register ce d clk q enable delay register d clk q bwe bwd ce (t,d) ce2 (t) ce2 (t,d) bwb bwc 256k x 32; 256k x 36; 512k x 18 memory array input registers clk 32, 36, or 18 oe 4 oe dqa - dqd 18/19 a (x32/x36) (x32/x36/x18) (x32/x36) (x32/x36/x18) 32, 36, or 18 32, 36, or 18
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? pin configuration 119-pin pbga (top view) (d version) 256k x 32 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable a b c d e f g h j k l m n p r t u v ddq nc nc dqc dqc v ddq dqc dqc v ddq dqd dqd v ddq dqd dqd nc nc v ddq a ce2 a nc dqc dqc dqc dqc v dd dqd dqd dqd dqd nc a nc nc a a a gnd gnd gnd bwc gnd nc gnd bwd gnd gnd gnd mode a nc adsp adsc v dd nc ce oe adv gw v dd clk nc bwe a1 a0 v dd a nc a a a gnd gnd gnd bwb gnd nc gnd bwa gnd gnd gnd gnd a nc a a a nc dqb dqb dqb dqb v dd dqa dqa dqa dqa nc a nc nc v ddq nc nc dqb dqb v ddq dqb dqb v ddq dqa dqa v ddq dqa dqa nc zz v ddq 1 2 3 4 5 6 7 nc dqb dqb v ddq gnd dqb dqb dqb dqb gnd v ddq dqb dqb gnd nc v dd zz dqa dqa v ddq gnd dqa dqa dqa dqa gnd v ddq dqa dqa nc nc dqc dqc v ddq gnd dqc dqc dqc dqc gnd v ddq dqc dqc nc v dd nc gnd dqd dqd v ddq gnd dqd dqd dqd dqd gnd v ddq dqd dqd nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd v dd nc nc a a a a a a a 46 47 48 49 50 a a ce ce2 bwd bwc bwb bwa a v dd gnd clk gw bwe oe adsc adsp adv a a 256k x 32 100-pin tqfp (d version)
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? pin configuration 100-pin tqfp (t version) 256k x 32 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable nc dqb dqb v ddq gnd dqb dqb dqb dqb gnd v ddq dqb dqb gnd nc v dd zz dqa dqa v ddq gnd dqa dqa dqa dqa gnd v ddq dqa dqa nc nc dqc dqc v ddq gnd dqc dqc dqc dqc gnd v ddq dqc dqc nc v dd nc gnd dqd dqd v ddq gnd dqd dqd dqd dqd gnd v ddq dqd dqd nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd v dd nc a a a a a a a a 46 47 48 49 50 a a ce ce2 bwd bwc bwb bwa ce2 v dd gnd clk gw bwe oe adsc adsp adv a a
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd individual byte write enable bwe synchronous byte write enable tms, tdi jtag boundry scan pins tck, tdo gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode bu rst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o 256k x 36 100-pin tqfp (d version) dqpb dqb dqb v ddq gnd dqb dqb dqb dqb gnd v ddq dqb dqb gnd nc v dd zz dqa dqa v ddq gnd dqa dqa dqa dqa gnd v ddq dqa dqa dqpa dqpc dqc dqc v ddq gnd dqc dqc dqc dqc gnd v ddq dqc dqc nc v dd nc gnd dqd dqd v ddq gnd dqd dqd dqd dqd gnd v ddq dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd v dd nc nc a a a a a a a 46 47 48 49 50 a a ce ce2 bwd bwc bwb bwa a v dd gnd clk gw bwe oe adsc adsp adv a a 256k x 36 pin configuration 100-pin tqfp (t version) dqpb dqb dqb v ddq gnd dqb dqb dqb dqb gnd v ddq dqb dqb gnd nc v dd zz dqa dqa v ddq gnd dqa dqa dqa dqa gnd v ddq dqa dqa dqpa dqpc dqc dqc v ddq gnd dqc dqc dqc dqc gnd v ddq dqc dqc nc v dd nc gnd dqd dqd v ddq gnd dqd dqd dqd dqd gnd v ddq dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd v dd nc a a a a a a a a 46 47 48 49 50 a a ce ce2 bwd bwc bwb bwa ce2 v dd gnd clk gw bwe oe ads c adsp adv a a
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? pin configuration 119-pin pbga (top view) (d version) 256k x 36 pin configuration 119-pin pbga (top view) (j version) a b c d e f g h j k l m n p r t u v ddq nc nc dqc dqc v ddq dqc dqc v ddq dqd dqd v ddq dqd dqd nc nc v ddq a ce2 a dqpc dqc dqc dqc dqc v dd dqd dqd dqd dqd dqpd a nc nc a a a gnd gnd gnd bwc gnd nc gnd bwd gnd gnd gnd mode a nc adsp adsc v dd nc ce oe adv gw v dd clk nc bwe a1 a0 v dd a nc a a a gnd gnd gnd bwb gnd nc gnd bwa gnd gnd gnd gnd a nc a a a dqpb dqb dqb dqb dqb v dd dqa dqa dqa dqa dqpa a nc nc v ddq nc nc dqb dqb v ddq dqb dqb v ddq dqa dqa v ddq dqa dqa nc zz v ddq 1 2 3 4 5 6 7 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd individual byte write enable bwe synchronous byte write enable tms, tdi jtag boundry scan pins tck, tdo gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode bu rst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o a b c d e f g h j k l m n p r t u v ddq nc nc dqc dqc v ddq dqc dqc v ddq dqd dqd v ddq dqd dqd nc nc v ddq a ce2 a dqpc dqc dqc dqc dqc v dd dqd dqd dqd dqd dqpd a nc tms a a a gnd gnd gnd bwc gnd nc gnd bwd gnd gnd gnd mode a tdi adsp adsc v dd nc ce oe adv gw v dd clk nc bwe a1 a0 v dd a tck a a a gnd gnd gnd bwb gnd nc gnd bwa gnd gnd gnd gnd a tdo a a a dqpb dqb dqb dqb dqb v dd dqa dqa dqa dqa dqpa a nc nc v ddq nc nc dqb dqb v ddq dqb dqb v ddq dqa dqa v ddq dqa dqa nc zz v ddq 1 2 3 4 5 6 7 256k x 36
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? 119-pin pbga (top view) (j version) a b c d e f g h j k l m n p r t u v ddq nc nc dqb nc v ddq nc dqb v ddq nc dqb v ddq dqb nc nc nc v ddq a ce2 a nc dqb nc dqb nc v dd dqb nc dqb nc dqpb a a tms a a a gnd gnd gnd bwb gnd nc gnd gnd gnd gnd gnd mode a tdi adsp adsc v dd nc ce oe adv gw v dd clk nc bwe a1 a0 v dd nc tck a a a gnd gnd gnd gnd gnd nc gnd bwa gnd gnd gnd gnd a tdo a a a dqpa nc dqa nc dqa v dd nc dqa nc dqa nc a a nc v ddq nc nc nc dqa v ddq dqa nc v ddq dqa nc v ddq nc dqa nc zz v ddq 1 2 3 4 5 6 7 pin configuration 119-pin pbga (top view) (d version) 512k x 18 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd individual byte write enable bwe synchronous byte write enable tms, tdi jtag boundry scan pins tck, tdo gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode bu rst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o 512k x 18 a b c d e f g h j k l m n p r t u v ddq nc nc dqb nc v ddq nc dqb v ddq nc dqb v ddq dqb nc nc nc v ddq a ce2 a nc dqb nc dqb nc v dd dqb nc dqb nc dqpb a a nc a a a gnd gnd gnd bwb gnd nc gnd gnd gnd gnd gnd mode a nc adsp adsc v dd nc ce oe adv gw v dd clk nc bwe a1 a0 v dd nc nc a a a gnd gnd gnd gnd gnd nc gnd bwa gnd gnd gnd gnd a nc a a a dqpa nc dqa nc dqa v dd nc dqa nc dqa nc a a nc v ddq nc nc nc dqa v ddq dqa nc v ddq dqa nc v ddq nc dqa nc zz v ddq 1 2 3 4 5 6 7
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? 512k x 18 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd individual byte write enable bwe synchronous byte write enable tms, tdi jtag boundry scan pins tck, tdo gw synchronous global write enable ce , ce2, ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o a nc nc v ddq gnd nc dqpa dqa dqa gnd v ddq dqa dqa gnd nc v dd zz dqa dqa v ddq gnd dqa dqa nc nc gnd v ddq nc nc nc a a ce ce2 nc nc bwb bwa ce2 v dd gnd clk gw bwe oe adsc adsp adv a a nc nc nc v ddq gnd nc nc dqb dqb gnd v ddq dqb dqb gnd v dd nc gnd dqb dqb v ddq gnd dqb dqb dqpb nc gnd v ddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd v dd nc a a a a a a a a 46 47 48 49 50 100-pin tqfp (t version) a nc nc v ddq gnd nc dqpa dqa dqa gnd v ddq dqa dqa gnd nc v dd zz dqa dqa v ddq gnd dqa dqa nc nc gnd v ddq nc nc nc a a ce ce2 nc nc bwb bwa a v dd gnd clk gw bwe oe adsc adsp adv a a nc nc nc v ddq gnd nc nc dqb dqb gnd v ddq dqb dqb gnd v dd nc gnd dqb dqb v ddq gnd dqb dqb dqpb nc gnd v ddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd v dd nc nc a a a a a a a 46 47 48 49 50 pin configuration 100-pin tqfp (d version) 512k x 18
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? partial truth table function gw gw gw gw gw bwe bwe bwe bwe bwe bwa bwa bwa bwa bwa bwb bwb bwb bwb bwb bwc bwc bwc bwc bwc bwd bwd bwd bwd bwd read h h xxxx read h l hhhh write byte 1 h l l h h h write all bytes hlllll write all bytes lxxxxx truth table address operation used ce ce ce ce ce ce2 ce2 ce2 ce2 ce2 ce2 adsp adsp adsp adsp adsp adsc adsc adsc adsc adsc adv adv adv adv adv write write write write write oe oe oe oe oe dq deselected, power-down none h x x x l x x x high-z deselected, power-down none l x h l x x x x high-z deselected, power-down none l l x l x x x x high-z deselected, power-down none l x h h l x x x high-z deselected, power-down none l l x h l x x x high-z read cycle, begin burst e xternal l h l l x x x x q read cycle, begin burst e xternal l h l h l x read x q write cycle, begin burst e xternal l h l h l x w rite x d read cycle, continue burst next x x x h h l read l q read cycle, continue burst next x x x h h l read h high-z read cycle, continue burst next h x x x h l read l q read cycle, continue burst next h x x x h l read h high-z write cycle, continue burst next x x x h h l write x d write cycle, continue burst next h x x x h l write x d read cycle, suspend burst current x x x h h h read l q read cycle, suspend burst current x x x h h h read h high-z read cycle, suspend burst current h x x x h h read l q read cycle, suspend burst current h x x x h h read h high-z write cycle, suspend burst current x x x h h h w rite x d write cycle, suspend burst current h x x x h h w rite x d
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? interleaved burst address table (mode = v ddq or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd q ) absolute maximum ratings (1) symbol parameter value unit t stg storage temperature ?55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ?0.5 to v ddq + 0.3 v v in voltage relative to gnd for ?0.5 to v dd + 0.5 v for address and control inputs v dd voltage on vdd supply relatiive to gnd ?0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v, +10%, ?5% 2.375 ? 3.6v industrial ?40c to +85c 3.3v, +10%, ?5% 2.375 ? 3.6v dc electrical characteristics (1) (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage i oh = ?1.0 ma, v ddq = 2.5v 2.0 ? v i oh = ?4.0 ma, v ddq = 3.3v 2.4 ? v v ol output low voltage i ol = 1.0 ma, v ddq = 2.5v ? 0.4 v i ol = 8.0 ma, v ddq = 3.3v ? 0.4 v v ih input high voltage v ddq = 2.5v 1.7 v dd + 0.3 v v ddq = 3.3v 2.0 v dd + 0.3 v v il input low voltage v ddq = 2.5v ?0.3 0.7 v v ddq = 3.3v ?0.3 0.8 v i li input leakage current gnd v in v ddq (2) com. ?5 5 a ind. ?5 5 i lo output leakage current gnd v out v ddq , oe = v ih com. ?5 5 a ind. ?5 5 power supply characteristics (over operating range) 6.5 7.5 symbol parameter test conditions max. max. uni t i cc ac operating device selected, com. 110 100 ma supply current all inputs < v il or > v ih ind. 120 110 ma oe = v ih , zz < v il cycle time t kc min. i sb standby current device deselected, com. 55 55 ma v dd = max., ind. 60 60 ma all inputs < v il or > v ih zz < v il , f = fmax i sbi standby current device deselected, com. 30 30 ma cmos input v dd = max., ind. 40 40 ma v in gnd + 0.2v or v dd -0.2v f = 0 notes: 1. the mode pin should be tied to v dd or gnd. it exhibits 30 a maximum leakage current when tied to < gnd + 0.2v or v dd ? 0.2v.
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1ns input and output timing 1.5v and reference level output load see figures 1 and 2 figure 1 figure 2 capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, vdd = 3.3v. 3.3v i/o output load equivalent z o = 50 ? 1.5v 50 ? ? 5 pf including jig and scope 351 ? output +3.3v
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1 ns input and output timing 1.25v and reference level output load see figures 3 and 4 figure 3 figure 4 2.5v i/o output load equivalent z o = 50 ? 1.25v 50 ? ? 5 pf including jig and scope 1,538 ? output +2.5v
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? read/write cycle switching characteristics (over operating range) 6.5 7.5 symbol parameter min. max. min. max. unit f max clock frequency ? 133 ? 117 mhz t kc cycle time 7.5 ? 8.5 ? ns t kh clock high pulse width 2.2 ? 2.5 ? ns t kl clock low pulse width 2.2 ? 2.5 ? ns t kq clock access time ? 6.5 ? 7.5 ns t kqx (1) clock high to output invalid 2 ? 2 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? ns t kqhz (1,2) clock high to output high-z ? 3.5 ? 3.5 ns t oeq output enable to output valid ? 3.5 ? 3.5 ns t oelz (1,2) output enable to output low-z 0 ? 0 ? ns t oehz (1,2) output enable to output high-z ? 3.5 ? 3.5 ns t as address setup time 1.5 ? 1.8 ? ns t ss address status setup time 1.5 ? 1.8 ? ns t ws write setup time 1.5 ? 1.8 ? ns t ces chip enable setup time 1.5 ? 1.8 ? ns t avs address advance setup time 1.5 ? 1.8 ? ns t ah address hold time 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? ns note: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? read/write cycle timing single read flow-through single write high-z high-z data out data in oe ce2 ce2 ce bwd-bwa bwe gw a adv adsc adsp clk rd1 wr1 wr1 1a 1a 2a 2b 2c 2d unselected burst read t kqx t kc t kl t kh t ss t sh adsp is blocked by ce inactive t ss t sh t as t ah t ws t wh t ws t wh t ws t wh rd2 rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeqx t kq t oehz t kqx t kqhz t ds t dh t kqhz t kqlz
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? write cycle switching characteristics (over operating range) 6.5 7.5 symbol parameter min. max. min. max. unit t kc cycle time 7.5 ? 8.5 ? ns t kh clock high pulse width 2.0 ? 2.5 ? ns t kl clock low pulse width 2.2 ? 2.5 ? ns t as address setup time 1.5 ? 1.8 ? ns t ss address status setup time 1.5 ? 1.8 ? ns t ws write setup time 1.5 ? 1.8 ? ns t ds data in setup time 1.5 ? 1.8 ? ns t ces chip enable setup time 1.5 ? 1.8 ? ns t avs address advance setup time 1.5 ? 1.8 ? ns t ah address hold time 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? ns t dh data in hold time 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? ns
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? write cycle timing single write data out data in oe ce2 ce2 ce bwd-bwa bwe gw a17-a0 adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce3 only sampled with adsp or adsc ce1 masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce1 inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2b 2a
18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? sleep mode timing don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (except zz) outputs (q) i sb2 zz setup cycle zz recovery cycle normal operation cycle t pds t pus t zzi high-z sleep mode electrical characteristics symbol parameter cond itions min. max. unit i sb 2 current during sleep mode zz v ih com. ? 30 ma zz v ih ind. ? 40 t pds zz active to input ignored 2 ? cycle t pus zz inactive to input sampled 2 ? cycle t zzi zz active to sleep current 2 ? cycle t rzzi zz inactive to exit sleep current 0 ? ns
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? 31 30 29 . . . 2 1 0 2 1 0 0 x . . . . . 2 1 0 bypass register instruction register identification register boundary scan register* tap controller selection circuitry selection circuitry tdo tdi tck tms ieee 1149.1 serial boundary scan (jtag) the is61lf25636t/d/j and is61lf51218t/d/jt/d/jt/d/ j have a serial boundary scan test access port (tap) in the pbga package only. (not available in tqfp package or with the is61lps25632t/d/j.) this port operates in accor- dance with ieee standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because they place added delay in the critical speed path of the sram. the tap controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 2.5v i/o logic levels. disabling the jtag feature the sram can operate without using the jtag feature. to disable the tap controller, tck must be tied low (gnd) to prevent clocking of the device. tdi and tms are internally pulled up and may be disconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left disconnected. on power-up, the device will start in a reset state which will not interfere with the device operation. test access port (tap) - test clock the test clock is only used with the tap controller. all inputs are captured on the rising edge of tck and outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. this pin may be left disconnected if the tap is not used. the pin is internally pulled up, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information to the registers and can be connected to the input of any register. the register between tdi and tdo is chosen by the instruction loaded into the tap instruction register. for information on instruction register loading, see the tap controller state diagram. tdi is internally pulled up and can be disconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. tap controller block diagram
20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending on the current state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck and tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at power-up, the tap is internally reset to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry . only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the in- struction register. this register is loaded when it is placed between the tdi and tdo pins. (see tap controller block diagram) at power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as previously described. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (gnd) when the bypass instruction is ex- ecuted. boundary scan register the boundary scan register is connected to all input and output pins on the sram . several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 configuration has a 70-bit-long register and the x18 configuration has a 51-bit-long regis- ter. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and then placed bet ween the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. scan register sizes register name bit size (x18) bit size (x36) instruction 3 3 bypass 1 1 id 32 32 boundary scan 51 70
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register contents die vendor issi technology revision part configuration defomotopm jedec vendor code id code presence register part #31302928 2726 2524 2322 212019 1817 161514 1312 1110 9 8 7 6 5 4 3 2 1 0 256k x x x x 0 0 1 1 0 0 0 1 0 0 x x x x x x 0 0 0 1 1 0 1 0 1 0 1 1 512k x x x x 0 0 1 1 1 0 0 0 1 1 x x x x x x 0 0 0 1 1 0 1 0 1 0 1 1 sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not imple- mented, so the tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded to the instruction register and the tap controller is in the capture- dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. it is important to realize that the tap controller clock operates at a frequency up to 10 mhz, while the sram clock runs more than an order of magnitude faster. because of the clock frequency differences, it is possible that during the capture-dr state, an input or output will under-go a transition. the tap may attempt a signal capture while in transition (metastable state). the device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. to guarantee that the boundary scan register will capture the correct signal value, the sram signal must be stabi- lized long enough to meet the tap controller?s capture set- up plus hold times (t cs and t ch ). to insure that the sram clock input is captured correctly, designs need a way to stop (or slow) the clock during a sample/preload instruc- tion. if this is not an issue, it is possible to capture all other signals and simply ignore the value of the clk and clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are con- nected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
22 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? instruction codes code instruction description 001 idcode loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. 010 sample z captures the input/output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. 011 reserved do not use: this instruction is reserved for future use. 100 sample/preload captures the input/output ring contents. places the boundary scan register be- tween tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 reserved do not use: this instruction is reserved for future use. 110 reserved do not use: this instruction is reserved for future use. 111 bypass places the bypass register between tdi and tdo. this operation does not affect sram operation. tap controller state diagram select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test/idle 11 1 11 11 1 1 1 1 1 1 1 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 10
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 23 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? tap electrical characteristics over the operating range (1,2) symbol parameter test conditions mi n. max. units v oh1 output high voltage i oh = ?2.0 ma 1.7 ? v v oh2 output high voltage i oh = ?100 ma 2.1 ? v v ol1 output low voltage i ol = 2.0 ma ? 0.7 v v ol2 output low voltage i ol = 100 ma ? 0.2 v v ih input high voltage 1.7 v dd +0.3 v v il input low voltage i olt = 2ma ?0.3 0.7 v i x input load current gnd v i v ddq ?5 5 ma notes: 1. all voltage referenced to ground. 2. overshoot: v ih (ac) v dd +1.5v for t t tcyc /2, undershoot:v il (ac) 0.5v for t t tcyc /2, power-up: v ih < 2.6v and v dd < 2.4v and v ddq < 1.4v for t < 200 ms. tap ac electrical characteristics (1) (over operating range) symbol parameter min. max. unit t tcyc tck clock cycle time 100 ? ns f tf tck clock frequency ? 10 mhz t th tck clock high 40 ? ns t tl tck clock low 40 ? ns t tmss tms setup to tck clock rise 10 ? ns t tdis tdi setup to tck clock rise 10 ? ns t cs capture setup to tck rise 10 ? ns t tmsh tms hold after tck clock rise 10 ? ns t tdih tdi hold after clock rise 10 ? ns t ch capture hold after clock rise 10 ? ns t tdov tck low to tdo valid ? 20 ns t tdox tck low to tdo invalid 0 ? ns notes: 1. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
24 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? tap timing tap output load equivalent tap ac test conditions input pulse levels 0 to 2.5v input rise and fall times 1ns input timing reference levels 1.25v output reference levels 1.25v test load termination supply voltage 1.25v 20 pf tdo gnd 50 ? 1.25v z 0 = 50 ? don't care undefined tck tms tdi tdo t thtl t tlth t thth t mvth t thmx t dvth t thdx 1 2 3 4 5 6 t tlox t tlov
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 25 rev.a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? boundary scan order (256k x 36) signal bump signal bump signal bump signal bump bit # name id bit # name id bit # name id bit # name id 1 a 2r 19 dqb 7g 37 bwa 5l 55 dqd 2k 2 a 3t 20 dqb 6f 38 bwb 5g 56 dqd 1l 3 a 4t 21 dqb 7e 39 bwc 3g 57 dqd 2m 4 a 5t 22 dqb 7d 40 bwd 3l 58 dqd 1n 5 a 6r 23 dqb 7h 41 ce2 2b 59 dqd 1p 6 a 3b 24 dqb 6g 42 ce 4e 60 dqd 1k 7 a 5b 25 dqb 6e 43 a 3a 61 dqd 2l 8 dqa 6p 26 dqb 6d 44 a 2a 62 dqd 2n 9 dqa 7n 27 a 6a 45 dqc 2d 63 dqd 2p 10 dqa 6m 28 a 5a 46 dqc 1e 64 mode 3r 11 dqa 7l 29 adv 4g 47 dqc 2f 65 a 2c 12 dqa 6k 30 adsp 4a 48 dqc 1g 66 a 3c 13 dqa 7p 31 adsc 4b 49 dqc 2h 67 a 5c 14 dqa 6n 32 oe 4f 50 dqc 1d 68 a 6c 15 dqa 6l 33 bwe 4m 51 dqc 2e 69 a1 4n 16 dqa 7k 34 gw 4h 52 dqc 2g 70 a0 4p 17 zz 7t 35 clk 4k 53 dqc 1h 18 dqb 6h 36 a 6b 54 nc 5r boundary scan order (512k x 18) signal bump signal bump signal bump signal bump bit # name id bit # name id bit # name id bit # name id 1 a 2r 14 dqa 7g 27 clk 4k 40 dqb 2k 2 a 2t 15 dqa 6f 28 a 6b 41 dqb 1l 3 a 3t 16 dqa 7e 29 bwa 5l 42 dqb 2m 4 a 5t 17 dqa 6d 30 bwb 3g 43 dqb 1n 5 a 6r 18 a 6t 31 ce2 2b 44 dqb 2p 6a3b 19a6a 32 ce 4e 45 mode 3r 7 a 5b 20 a 5a 33 a 3a 46 a 2c 8 dqa 7p 21 adv 4g 34 a 2a 47 a 3c 9 dqa 6n 22 adsp 4a 35 dqb 1d 48 a 5c 10 dqa 6l 23 adsc 4b 36 dqb 2e 49 a 6c 11 dqa 7k 24 oe 4f 37 dqb 2g 50 a1 4n 12 zz 7t 25 bwe 4m 38 dqb 1h 51 a0 4p 13 dqa 6h 26 gw 4h 39 nc 5r
26 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 10/06/02 is61lf25632t/d/j is61lf25636t/d/j is61lf51218t/d/j issi ? ordering information commercial range: 0c to +70c speed order part number package 6.5 ns is61lf25632t-6.5tq tqfp is61lf25632d-6.5tq tqfp 7.5 ns is61lf25632t-7.5tq tqfp is61lf25632d-7.5tq tqfp is61lf25632d-7.5b pbga industrial range: ?40c to +85c speed order part number package 6.5 ns is61lf25632t-6.5tqi tqfp is61lf25632d-6.5tqi tqfp 7.5 ns is61lf25632t-7.5tqi tqfp is61lf25632d-7.5tqi tqfp industrial range: ?40c to +85c speed order part number package 6.5 ns is61lf25636t-6.5tqi tqfp is61lf25636d-6.5tqi tqfp 7.5 ns is61lf25636t-7.5tqi tqfp is61lf25636d-7.5tqi tqfp is61lf25636d-7.5bi tqfp is61lf25636j-7.5bi tqfp industrial range: ?40c to +85c speed order part number package 6.5 ns is61lf51218t-6.5tqi tqfp is61lf51218d-6.5tqi tqfp 7.5 ns is61lf51218t-7.5tqi tqfp is61lf51218d-7.5tqi tqfp is61lf51218d-7.5bi tqfp is61lf51218j-7.5bi tqfp commercial range: 0c to +70c speed order part number package 6.5 ns is61lf25636t-6.5tq tqfp is61lf25636d-6.5tq tqfp is61lf25636d-6.5b pbga is61lf25636j-6.5b pbga 7.5 ns is61lf25636t-7.5tq tqfp is61lf25636d-7.5tq tqfp is61lf25636d-7.5b pbga is61lf25636j-7.5b pbga commercial range: 0c to +70c speed order part number package 6.5 ns is61lf51218t-6.5tq tqfp is61lf51218d-6.5tq tqfp is61lf51218d-6.5b pbga is61lf51218j-6.5b pbga 7.5 ns is61lf51218t-7.5tq tqfp is61lf51218d-7.5tq tqfp is61lf51218d-7.5b pbga is61lf51218j-7.5b pbga

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